Abstract: High speed, low power consumption are key requirement to any VLSI design. The power efficient multipliers play an important role. This paper presents an efficient implementation of a high speed, low power Baugh-Wooley multiplier using aging aware technique and adaptive hold logic. This study presented the design and implementation of Baugh Wooely multipliers using XILINX. In this work, Modified Baugh Wooley is having least area, power and delay. The Modified Baugh Wooley architecture with adaptive hold logic and aging awareness make this efficient and also reliable. 32 bit signed multiplication and fractional multiplication is carried out and verified with around 10000 test patterns.

Keywords: Low Power, Multiplier, Baugh-Wooley, Precision, Aging Aware, Adaptive hold.